A finFET includes a source-channel-drain region (the fin) around which is formed a gate. Activation of the gate, source and drain facilitates current drivability in the channel between the source and the drain, thereby facilitating operation of the finFET.
In finFET technologies at 14 nm node and beyond, the structure of the fin is critical for device performance. Narrow fin width in the range of 5 to 10 nm is a key requirement/feature which benefits the control of the short-channel effect (SCE) and enhancement of transistor performance. With conventional techniques, however, a trapezoid-shaped fin results due to fin etch processing. For example, a conventional fin having a height of 30 nm will have a top portion of 5 to 7 nm in width and a bottom portion of 14 to 16 nm thick. Thus, the bottom portion of the fin is always thicker than a top portion of the fin and results in a fin body control delta between the top and bottom portions. A punch-through-stop (PTS) implant is commonly used for control the fin bottom SCE.
Replacement metal gate (RMG) processing is commonly used in finFET technology. Uniform metal material with RMG processing is a key requirement for reliable device characteristics. However, considering the trapezoid-shaped fin and non-uniform doping, in order to optimize device design, the RMG gate design also needs to be adjusted/controlled to ensure reliable device characteristics.
A need therefore exists for methodology that adjusts/controls RMG design taking into consideration trapezoid-shaped fins, and improves the performance of resulting devices.